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Comparison of multiplier implementations in a logarithmic number system

Marjana Erdelji (2010) Comparison of multiplier implementations in a logarithmic number system. MSc thesis.

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    The master's thesis discusses binary multipliers. Reported in detail are multipliers suitable for digital signal processing applications. Digital signal processing algorithms often rely heavily on a large number of multiplications, which is both time and power consuming. There are many practical solutions to simplify multiplication, like truncated and logarithmic multipliers, which consume less time and power, but introduce errors. Nevertheless, they can be used in situations where a shorter time delay is more important than accuracy. The thesis presents multipliers in a logarithmic number system. Following arithmetically inexact multipliers were compared against speed, resources required for implementation, power consumption and error rate: Mitchell's algorithm based multiplier (MA), operand decomposition based multiplier (OD-MA) and a simple iterative multiplier (SIM). Error analysis of these multipliers was made. Through a SIM iterative procedure it is possible to achieve an arbitrary accuracy. For the hardware implementation assessment, the multipliers were implemented on the Spartan3 and Virtex6 Low Power FPGA chip. The hardware solution involves adders and shifters, so it is not gate and power consuming. These arithmetically inexact multipliers were also compared with arithmetically exact array multiplier based on all before mentioned criteria. Pipelined hardware implementation of all these multipliers was made. The results show how simplifying the implementation of multipliers lowers required resurces, speeds up the implementation and reduces power consumption, but at the expense of increased error rate. Smoothing images application, based on convolution of image and convolution mask, was used to determine how comparable is error generated by arithmetically unexact multipliers with error generated by the image conversion from bmp to jpg format. Unexact multipliers are therefore useful in applications that allow a ceratin percentage of error tolerance.

    Item Type: Thesis (MSc thesis)
    Keywords: computer arithmetic, binary multiplication, digital signal processing, logarithmic number system, FPGA
    Number of Pages: 77
    Language of Content: Slovenian
    Mentor / Comentors:
    Name and SurnameIDFunction
    doc. dr. Patricio Bulić255Mentor
    Link to COBISS: http://www.cobiss.si/scripts/cobiss?command=search&base=50070&select=(ID=00007962452)
    Institution: University of Ljubljana
    Department: Faculty of Computer and Information Science
    Item ID: 1153
    Date Deposited: 30 Aug 2010 14:54
    Last Modified: 13 Aug 2011 00:37
    URI: http://eprints.fri.uni-lj.si/id/eprint/1153

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