Borut Rifelj (2009) Connection of cellular automattion with the OpenRISC processor. EngD thesis.
The bachelor’s thesis describes implementation of a system that connects the microprocessor OpenRISC 1200 and cellular automata. The system is written in the Verilog HDL language. At the beginning of the work the structure of the modules contained in the system is described. It is followed by a description of the system and the results. The main part of the system is scalar microprocessor OpenRISC 1200, which uses the memory and cellular automata. In memory commands are stored, which are read by the microprocessor. The cellular automation is implemented as a separate peripheral module. The microprocessor, using an appropriate command and the corresponding address information, sends data to cellular automaton, which processes the data. After completing the processing, the data is ready to be read by the microprocessor. The implementation is based on the WISHBONE bus, which connects all the main elements of the system. Since the system includes two masters and two slaves, the selected topology is the shared bus. The implementation includes a master-select logic for selecting the master, based on the CYC signal, and a slave-select logic for selection of a slave, based on a separate address space.
|Item Type: ||Thesis (EngD thesis)|
|Keywords: ||• microprocessor OpenRISC 1200 • memory controller • SDRAM • cellular automata • WISHBONE bus|
|Number of Pages: ||54|
|Language of Content: ||Slovenian|
|Mentor / Comentors: |
|Name and Surname||ID||Function|
|izr. prof. dr. Branko Šter||283||Mentor|
|Link to COBISS: ||http://www.cobiss.si/scripts/cobiss?command=search&base=50070&select=(ID=)|
|Institution: ||University of Ljubljana|
|Department: ||Faculty of Computer and Information Science|
|Item ID: ||929|
|Date Deposited: ||08 Oct 2009 08:42|
|Last Modified: ||13 Aug 2011 00:36|
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