ePrints.FRI - University of Ljubljana, Faculty of Computer and Information Science

Implementation of a memory interface in FPGA

Matevž Bizjak (2012) Implementation of a memory interface in FPGA. EngD thesis.

Download (8Mb)


    There are certain computational problems, where processing data using general purpose computer processing units is ineffective and time-consuming. FPGA (Field-Programmable Gate Array) integrated circuits allow designers configuring their operations for specific problems. This way, data can be processed on a hardware level. The purpose of this thesis is to design and implement a solution that will allow sending data from computer to FPGA and saving it in RAM (Random Access Memory), which is embeded in the FPGA development board. No logic, that could process data on FPGA will be implemented. Two Xilinx FPGA development boards are used for the purpose of this thesis - a simple board based on Spartan-3A FPGA family and an advanced board based on Virtex-6 family. It turns out that Spartan-3A based development board is unsuitable for the intended design, therefore Virtex-6 based board is used. The thesis describes the implementation of memory controller using MIG (Memory Interface Generator) tool, the implementation of module, which allows serial communication with the FPGA board and connection of both modules with logic, that controls the complete design. A graphical user interface, that allows selecting an input file, sending it to FPGA and writing processed data to output file is also designed. Design simulation and practical testing of designed solution confirm that interfacing RAM with Xilinx FPGA development boards is user friendly and efficient. We come to the conclusion that serial transmission of data is slow, so additional improvements could be made in this field. The final design could easily be upgraded with processing logic that would process received data from computer.

    Item Type: Thesis (EngD thesis)
    Keywords: FPGA, DDR SDRAM memory, memory controller, serial communication, UART, graphical user interface
    Number of Pages: 69
    Language of Content: Slovenian
    Mentor / Comentors:
    Name and SurnameIDFunction
    prof. dr. Patricio Bulić255Mentor
    Link to COBISS: http://www.cobiss.si/scripts/cobiss?command=search&base=50070&select=(ID=00009453652)
    Institution: University of Ljubljana
    Department: Faculty of Computer and Information Science
    Item ID: 1760
    Date Deposited: 05 Jul 2012 15:14
    Last Modified: 19 Oct 2012 10:08
    URI: http://eprints.fri.uni-lj.si/id/eprint/1760

    Actions (login required)

    View Item