The pipelined HIP processor in FPGA with the debugging environment

David Lapajne (2016) The pipelined HIP processor in FPGA with the debugging environment. EngD thesis.

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Abstract

This thesis describes the implementation of a central processing unit with pipeline called Hypothetical processor (HIP), which is described in book [1]. It contains logic for data forwarding, an adder for floating point numbers and it has an instruction and data cache. Through the debug unit it is possible to read from and write to all general and to other registers in the HIP pipeline and therefore monitor the flow of the compiled program. HIP runs in the FPGA chip on the Spartan 3E development board where supporting logic for monitoring is present. The external program written in Java runs on different operating systems. The monitoring program contains a text editor where it is possible to write in the assembler language. It also contains a compiler which translates an assembler code to HIP machine code. Operations and data are sent to the debug unit to HIP. Each clock cycle, the monitoring program reads the content of every register in the CPU. The content of the main memory and cache is seen too.

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